In conventional digital communication systems, information is transferred between sending and receiving terminals over a transmission line or, more generally, a communication channel in a format suitable for that channel. The format can be a baseband signal or, using a digitally modulated carrier, a bandpass signal. In either case, the signal is characterized by a fundamental bit rate, i.e., the clock frequency of the data.
In synchronous transmission typically used in computer-to-computer communication, for example, the receiving terminal determines the clock frequency of the sending terminal, e.g., for decoding purposes, by deriving a clock signal from timing information inherent in the communication signal, itself. This process is known as clock recovery. The recovered clock enables the receiving terminal to optimally sample the received digitally encoded communication signals during the decoding process. Clock recovery circuits commonly are employed, for instance, in conjunction with local area networks ("LAN's") and point-to-point communication links.
In such applications, the baseband signals typically are encoded in a unipolar return-to-zero ("unipolar RZ"), bipolar return-to-zero ("bipolar RZ"), nonreturn-to-zero ("NRZ") or other largely standardized format or waveform. The unipolar-RZ, bipolar-RZ and NRZ designations are well understood by those skilled in the data transmission art.
"Unipolar RZ" format is a digital code form having two information states, termed LOGIC ZERO and LOGIC ONE, and is characterized by the signal returning to LOGIC ZERO during each bit interval or window in which a LOGIC ONE is represented. Thus, in effect, LOGIC ZERO is the neutral condition or state. In other words, each positively directed transition or excursion from the neutral condition in unipolar-RZ-formatted signals indicates a LOGIC ONE, the signal returns to the neutral condition after each such positively directed transition and within the same bit interval, and the absence of a transition during a bit interval indicates LOGIC ZERO. Thus, each bit interval can contain a pulse representing a LOGIC ONE, or no pulse which indicates a LOGIC ZERO. In unipolar RZ-encoded communication signals, the frequency spectrum of the transmitted data includes a spectral component at the clock frequency (i.e., at the fundamental bit rate of the data).
"Bipolar RZ" is a digital code form having three states. For example, a known version has a positive state and a negative state which both represent LOGIC ONE's, and an intermediate state therebetween which represents a LOGIC ZERO and is the neutral condition. In other words, each positively or negatively directed transition in a bit interval indicates a LOGIC ONE, and within each such bit interval, after either the positively directed or negatively directed transition, the signal returns to the neutral condition. Put still another way, each bit interval in which a LOGIC ONE is represented has either a positive pulse or negative pulse extending from the neutral condition, and the signal is at the neutral condition at the boundaries of each such bit interval. In bipolar RZ-encoded communication signals, after full-wave rectification, the frequency spectrum of the received data includes a spectral component at the clock frequency (i.e., at the fundamental bit rate of the data).
"NRZ format" is a digital code form having only two states, termed LOGIC ZERO and LOGIC ONE. In a known version of NRZ-formatted signals, the voltage jumps positive, i.e., has a positively directly transition, to indicate LOGIC ONE and remains in that state during the entire bit interval as well as for all subsequent, contiguous bit intervals, if any, having a LOGIC ONE value; jumps negative, i.e., has a negatively directed transition, to indicate LOGIC ZERO and remains in that state during the entire bit interval as well as for all subsequent, contiguous bit intervals, if any, having a LOGIC ZERO value; and only jumps at the bit-interval-boundaries between LOGIC ONE and LOGIC ZERO, and vice versa, when the value correspondingly changes state. The value changes state at the positively and negatively directed transitions, which are collectively referred to as "signal crossings" or simply "transitions". An NRZ-encoded communication signal contains no actual spectral component at the clock frequency. The applicable clock frequency nonetheless can be derived from an NRZ-encoded signal by suitable clock recovery circuitry.
Clock recovery circuitry is responsible for deriving a clock signal equal in frequency to the bit rate of the transmitted message signal; or, phrased appropriately for unipolar- or full-wave rectified bipolar-RZ-formatted signals, clock recovery circuitry is responsible for recovery of the clock component contained or embedded in the received baseband signal, itself.
Conventional clock recovery circuits typically employ phase-locked loops ("PLL's"). A typical PLL has a voltage-controlled oscillator whose phase is locked onto a frequency component of its input signal. The PLL also has a phase detector for comparing the phase of the oscillator with the phase of the input signal, and for developing a voltage proportional to the phase differential, which commonly is referred to as a "phase error." This voltage is filtered and applied as a control voltage to the oscillator to adjust the oscillator's frequency. Due to negative feedback, the phase error is driven to a value which is preferably small, and the oscillator's frequency consequently is kept equal to the input frequency.
For various types of signal formats, the received signal is pre-processed before it is applied to the PLL for clock recovery. For bipolar RZ-formatted signals, for example, the received signals are first full-wave rectified before being applied to the PLL.
For NRZ-formatted signals, as another example, a transition detector circuit coupled in front of the PLL generates unipolar pulses at each signal crossing in the bit stream of the received signal, each pulse being within the bit window of the corresponding signal crossing of the received signal. In other words, the transition detector circuit generates a pulse corresponding to, and within the same bit interval as, each LOGIC-ZERO-to-LOGIC-ONE excursion (i.e., 0/1 transition) and each LOGIC-ONE-to-LOGIC-ZERO excursion (i.e., 1/0 transition). The output of the transition detector is a sequence of unipolar pulses, typically with gaps of varying lengths in between corresponding to bits in contiguous bit intervals having the same digital value. This output contains a clock frequency component. The PLL then generates a clock signal synchronized to this component.
PLL's used for clock recovery suffer a drawback of having a narrow pull-in range, i.e., such devices lock onto their input signals to derive a clock therefrom only when the input signals' bit rates fall within a narrow range centered about the clock frequency. For reliable operation, conventional recovery circuits using such PLL's typically must employ acquisition-aid circuitry. Acquisition-aid circuitry enables the PLL to reliably lock to the clock signal. Unfortunately, such acquisition aid circuitry can represent as much as half of the circuitry needed for clock recovery, and thus is costly in terms of circuit implementation, e.g., on I.C. chips in which space is typically at a premium. Additionally, the proper design and implementation of acquisition-aid circuitry can be costly in terms of engineering time and effort.
Another drawback of using a stand-alone PLL with acquisition-aid circuitry, as in the prior art, for recovering a clock is that the resulting clock signal is subject to systematic jitter which can reach undesirable levels, e.g., in cascaded clock recovery implementations.
Systematic jitter is undesired phase variations introduced within the PLL, and caused by fluctuations in the gain (typically expressed as volts/radian) of the phase detector. The phase detector gain varies as a function of transition density of the incoming bit stream for NRZ-formatted signals or of the LOGIC ONE density for unipolar or rectified bipolar RZ signals, and the densities vary in the short-term (i.e., over a time period on the order of the time constants of the PLL) due to the fact that the PLL input often does not contain a transition at the boundary of, or within, every bit interval. (For example, in NRZ-formatted signals, no transition occurs between contiguous LOGIC ZERO's or between contiguous LOGIC ONE's. Similarly, there is no transition or pulse in unipolar-RZ-formatted signals in bit intervals having a LOGIC ZERO value.) Thus, systematic jitter experienced in the prior art PLL-based clock recovery circuits is a result of the inherent characteristics of the encoded input signals to the PLL from which the clocks are to be recovered.
Examples of clock recovery circuits using PLL's are disclosed in U.S. Pat. Nos. 4,151,485, 4,180,783, 4,216,544, 4,575,860.
Another known type of clock recovery uses ringing circuits instead of PLL's. Ringing circuits for this purpose typically are configured for filtering, usually with a high Q-value, of either (i) the output of a transition detection circuit used for pre-processing NRZ-formatted signals, (ii) the full-wave rectified bipolar RZ-formatted signal, or (iii) directly of unipolar-RZ-formatted signals, themselves, to recover the clock signals. Unfortunately, such techniques typically are susceptible to filter mistuning, drift of the filter response over temperature, misalignments due to repeated temperature cycling, drift of the bit rate of the received data, and other problems, resulting in a discrepancy between the clock frequency and the center frequency of the ringing circuit. These problems combine in varying degrees and ultimately manifest themselves in the form of clock jitter.
Examples of this latter type of clock recovery circuit using filtering are disclosed in U.S. Pat. Nos. 4,222,117, 4,242,754, 4,339,824, 4,615,041, and 4,737,970.